Vacancies

Below are the list of vacancies currently available for applications. If interested, email your resume tojob@chromiumresources.com and desired position or contact 018-916 7300 for more inquiries.

Current positions open for application. Please refer below for more details.

  1. Sales Executive
  2. Product Manager
  3. Marketing Executive
  4. Data Scientist
  5. Mobile Engineer (IOS & Android)
  6. Machine Learning Engineer
  7. Analog IC Design Engineer
  8. Digital IC Design Engineer
  9. Custom Layout IC Design Engineer
  10. Application Development Lead
  11. Physical Design Engineer
  12. IO PHY Architect
Position Analog Integrated Circuit (I/C) Design Engineer
Location Petaling Jaya
Job Responsibilities • Design and development of  mixed-signal circuits such as High Speed Transmitters and Receivers, equalizers, DLL, clocking distribution, on die voltage regulators, Circuit Compensation Blocks and Voltage references blocks.
• Own design verification plans covering functional, performance and reliability meeting high volume productization requirement.
• Participate in circuit design review and work with Mask Designers on layout implementation and reviews
• Collaborate with design engineers of other disciple on integration of the analog circuit to the DDR PHY
• Mentoring of junior engineer
Job Qualifications • Proven track record on design of high speed analog and mixed-signal design, architecture, system and integration aspects for DDR PHYs
• Good Understanding of to LPDDR/DDR JEDEC specifications and related DDR Protocols
• Good understanding of design for yield and exposure to production challenges in latest technology process node
• Experience with industry standard tools for Analog design such as Cadence ADE, Spectre, AMS verification, FEV, StarRC etc..
• Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.
• Strong written and oral communication skills
• BSEE with 10+ years relevant experience or Master’s with 7+ years relevant experience required. Education Fo3005cus should include integrated circuit design and analog design.
Title Application Development Lead (IT)
Location Kuala Lumpur
Job Responsibilities Report to Head of IT. Lead application development team

o Identify and design application development solutions to support the organisation-wide common business needs.
o Gather and analyse user requirements on any application change request.
o Work closely with business users across departments and infrastructure team within department to ensure that design, development and implementation meets business requirement and any technical issues are resolved.
o Manage user training and user acceptance testing.
o Coordinate and monitor the progress of application change requests to ensure deliverables meet target dateline.
o Conduct research and development on business process and existing system to improve organization’s system while ensuring it keeps up date with the latest technology and best practices.
o Prepare periodic operational report and analysis in supporting continuous system improvement.

Job Qualifications • BSC Degree in Computer Science / Information Technology or equivalent.
• At least 2 year experience as a Team Lead to an application development team.
• At least 5 year experience as a System Analyst or Programmers.
• Application/Programming experience in these technologies: MySQL, GITHUB, HUDSON CI, PHP, Java OOP, Java MVC, Java Spring framework
• Strong problem solving and analytical skill.
• Strong understanding of relationship between applications, database and server operating systems environment.
• Familiar and experienced with Software Development Lifecycles (SDLC) and Application Testing procedures
• Ability to see a task through from assignment to completion with minimal supervision
• Willingness to keep up to date with developments in latest technology and best practices.
• An understanding of information legislation, such as the Personal Data Protection Act.
• Experience in education or insurance industry is an added advantage.
• Excellent written & spoken English & Bahasa Malaysia.
Title Digital Integrated Circuit (I/C) Design Engineer
Location Petaling Jaya
Job Descriptions o Scan RTL architecture, design and methodology
o Perform scan coverage analysis and debug with Spyglass-DFT or other ATPG tools
o Scan RTL and GLS test validation to ensure quality design
o Generate test patterns using industry standard tools, analyze and drive the improvements to test coverage
o Providing DFT constraints/exceptions to Static Timing Analysis (PV) and coordination of Scan/ATPG collaterals with IP provider
o Responsible for design/testing other part of design, including memory, mized signal, IO, custom LBIST + MBIST, 1149.1 JTAG.
o Partnership with post-Silicon High Volume Manufacturing (HVM) Team to enable Scan DFT test capability
o Collaborate with various stakeholders in architecture, IP, structural design, SoC RTL, and post-Silicon teams
o Understand DFT/Test architectures, integrate DFT infrastructure (TAP controller, Bscan, debug capability, loopback, pattern generator) into IP/SOC
o Implement DFT/Test in designs in the area of DFT Synthesis
Job Qualifications o 8 years’ experience in implementing DFT/Test in designs
o Understanding of DFT Infra, ATPG process, scan compression, MBIST,..
o Knowledge in RTL integration and validation methodologies
o Understanding of Scan/ATPG collaterals
o Familiar with Scan design, methodology, coverage analysis and test validation
o Tcl/Tk/Perl to automate design process and improve efficiency
o Knowledge of Synthesis/Scan stitching, STA, ATPG and MV design an advantage
o Knowledge of Synopsys DC/DFT Compiler, Primetime and UPF an advantage
o Familiar with UNIX, and well-versed in Verilog or C Programming
o Independent problem solving, debugging various simulation failures, formal verification etc.
o Ability to communicate well with counterparts and key stakeholders including cross-site partners
Title Custom Layout Integrated Circuit (I/C) Design Engineer
Location Petaling Jaya
Job Descriptions For > 3 years ( focus on execution skill)
• Design and development of mixed-signal analog layout such as High Speed Transmitters and Receivers, DLL, Clocking distribution, on die regulators and references blocks.
• Own layout verification covering design rule, High-Voltage, ESD Latch Up analysis, Reliability verification, design for manufacturing and yield improvement.
• Participate in Layout review with Circuit on layout implementation

For >8 years
o Lead, plan and execute complex IP layout efforts covering high-speed analog layout design and details drawing of VLSI semiconductor devices. Specify and drive layout tool and methodology enhancements aimed at improving layout productivity.

o Key responsibilities include but not limit to:
•  Design and development of mixed-signal analog layout such as High Speed Transmitters and Receivers, DLL, Clocking distribution, on die regulators and references blocks.
•  Own layout verification covering design rule, High-Voltage, ESD Latch Up analysis, Reliability verification, design for manufacturing and yield improvement.
• Participate in Layout review with Circuit on layout implementation
• Own layout work group to drive for analog layout efficiency
• 3005 Mentoring of junior engineer

Job Qualifications o Degree in Electrical or Electronic Engineering with minimum 4+ years in VLSI physical layout design.
o Experience in high-speed custom layout in 14nm and 10nm process node.
o Technical experience in hands-on Analog Custom Layout,
o proficient in floor planning, extraction, layout optimization and verification.
o Understanding of ESD (Electro Static Discharge), EM (Electro Migration) and DFM (Design for Manufacturing).
o BSc, MSc or PhD in Engineering with at least 15 years’ relevant experience.  The candidate should have strong analytical and management skills. Any relevant amount of experience would be an added advantage, including:
o Strong Architecture background in high speed mixed signal PHY >5Gbps. Serdes, die-to-die inter-connect and DDR.
o Expert on semi-con high speed IO PHY IP competitive roadmap.
o Expert on semi-con process competitive roadmap.
o Expert on SoC and Hard IP design methodology.Experience with industry standard tools for Analog such as Cadence Virtuoso would be an advantage
o Open to Malaysian Only
Title Physical Design Engineer
Location Petaling Jaya
Job Descriptions o Lead & Manage a group of Static Timing Analysis(STA)/Performance Validation(PV) engineers
o Working closely with Architecture and Design team to understand, define & generate timing specification/constraints
o Drive Implementation requirements (ie Clock Tree Synthesis targets), Influence & Continuous seek to improve the Timing Closure methodology, etc
o Drive timing closure, execute STA using industry tool (Primetime) and perform various quality check to ensure design converges on the timing sign-off requirements.
o Analyze timing report and proficient in using script to debug, automate tasks and provide timely feedback for timing ECO.
o Define and develop I/O budgets and drive for IP budget convergence.
o Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Job Qualifications You should possess a relevant educational qualification, BSEE or equivalent with 8+ years/MSEE or equivalent with 6+ years design experience in the structural/physical design domain. Additional qualifications include:
o Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
o Must have in depth, extensive knowledge and hands-on experience in Static timing analysis and timing signoff, including SDC development and timing budgeting.
o Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage
o Experienced in industry STA tools: Primetime and Primetime SI
o Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
o Experience of mentoring junior team members and charting their development for success.
Title IO PHY Architect/Manager
Location Petaling Jaya
Job Descriptions o Define the PHY architecture for next generation DDR and Die inter-connect to be competitive in market.
o Manage several senior technical analog micro-architect to define transistor level architecture.
o Work with analog and logic designers to understand the implementation impairments and trade-offs
o Interface with SoC and sub-system customers, package, platform, signal integrity and process teams
o Support post silicon and SoC lab debug and general investigations.
Job Qualifications o BSc, MSc or PhD in Engineering with at least 15 years’ relevant experience.
o The candidate should have strong analytical and management skills. Any relevant amount of experience would be an added advantage, including:
o Strong Architecture background in high speed mixed signal PHY >5Gbps. Serdes, die-to-die inter-connect and DDR.
o Expert on semi-con high speed IO PHY IP competitive roadmap.
o Expert on semi-con process competitive roadmap.
o Expert on SoC and Hard IP design methodology.
Title Sales Executive
Location Kuala Lumpur
Job Descriptions o Generate business revenue to meet targets set by the company
o Build close relationship with customers promptly and timely with precise information
o Attend all meetings set by sales administration timely with professional and pleasant personality
o Ensure professionalism in projecting the company’s image and when carrying out all duties, such as sales visit or during business proposition meetings followed by acknowledgements before the commencement job
o Actively participate in weekly sales meeting and provide reports to Sales Manager 
Title Product Manager
Location Kuala Lumpur
Job Descriptions o Identify potential sales, market opportunities and to position the company’s product.
o To encourage & motivates sales team to maximize their full potential and build strong teamwork and spirit
o To drive sales team to achieve Company’s goal and objectives and collection target
o Lead product definition for product releases, ensuring new products meet the prioritized clinical , operational, and financial needs of target customers.
o Play a leadership role in a multi-disciplinary team for new and sustaining product development
o Develop, maintain and clearly communicate a deep understanding of competitive strengths, weaknesses,  and strategic directions
Title Data Scientist
Location Kuala Lumpur
Job Descriptions o Research and develop statistical learning models for data analysis.
o Collaborate with product management and engineering departments to understand company needs and devise-possible.
o Keep up-to-date with latest technology trend.
o Communicate results and ideas to key decision.
o Continually create innovations in both analytic algorithms/methodologies and business improvements that translate to business impact.
o Responsible for the end-to-end process of analytical solution, business engagement, conceptualization, technical specification, model development and operational deployment.
Title Mobile Engineers (IOS & Android)
Location Kuala Lumpur
Job Descriptions o To design, develop, maintain mobile
applications according to requirement.
o Participate in initiatives that improve
processes that contribute to
performance effectiveness.
o Participate in brainstorming, sharing
idea and knowledge with the team
member.
o Perform any other job-related duties as
assigned.
Title Machine Learning Engineer
Location Kuala Lumpur
Job Descriptions o Utilizing data mining and machine
learning technologies , deep diving and
analysis of massive data
o Research bottlenecks of existing
algorithms and recommend
improvement measures and solutions.
o Involved in product failure repair,
optimization and technical support
related work
o Responsible for the development of
assigned module
o Maintain the code quality